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a ADP3164 5-bit programmable 4-phase synchronous buck controller functional block diagram features adopt? optimal positioning technology for superior load transient response and fewest output capacitors complies with vrm 9.1 with lowest system cost 4-phase operation at up to 500 khz per phase quad logic-level pwm outputs for interface to external high-power drivers active current balancing between all output phases accurate multiple vrm module current sharing 5-bit digitally programmable 1.1 v to 1.85 v output total output accuracy 0.8% over temperature current-mode operation short circuit protection enhanced power good output detects open outputs in multi-vrm power systems overvoltage protection crowbar protects microprocessors with no additional external components applications desktop pc power supplies for: intel pentium ? 4 processors vrm modules dac + 20% cmp csC cs+ comp fb g m pwm3 pwm1 set reset crowbar pgnd pwm2 vid dac vid4 vid3 vid2 vid1 vcc ref gnd ct vid0 share power good cmp dac C 20% pwrgd pwm4 3.0v reference uvlo & bias oscillator 4-phase driver logic ADP3164 soft start general description the ADP3164 is a highly efficient 4-phase synchronous buck switching regulator controller optimized for converting a 12 v main supply into the core supply voltage required by high per- formance intel processors. the ADP3164 uses an internal 5-bit dac to read a voltage identification (vid) code directly from the processor, which is used to set the output voltage between 1.1 v and 1.85 v. the ADP3164 uses a current mode pwm architecture to drive the logic-level outputs at a programmable switching frequency that can be optimized for vrm size and efficiency. the four output phases share the dc output current to reduce overall output voltage ripple. an active current bal- ancing function ensures that all phases carry equal portions of the total load current, even under large transient loads, to mini- mize the size of the inductors. the ADP3164 also uses a unique supplemental regulation tech- nique called active voltage positioning (adopt) to enhance load transient performance. active voltage positioning results in a dc/dc converter that meets the stringent output voltage specifi- cations for high-performance processors, with the minimum number of output capacitors and smallest footprint. unlike voltage-mode and standard current-mode architectures, active voltage positioning adjusts the output voltage as a function of the load current so that it is always optimally positioned for a system transient. the ADP3164 also provides accurate and reliable short circuit protection, adjustable current limiting, and an enhanced power good output that can detect open outputs in any phase for single or multi-vrm systems. the ADP3164 is specified over the commercial temperature range of 0 c to 70 c and is available in a 20-lead tssop package. pent i um i s a reg i stered trademark of intel corporat i on . revision history 01/08 rev 1: conversion to on semiconductor 010 scc rits reserved publication order number: may 2010 - rev. 2 ADP3164/d
rev. 0 C2C ADP3164Cspecifications 1 (vcc = 12 v, i ref = 150 a, t a = 0 c to 70 c, unless otherw i se noted.) parameter symbol conditions min typ max unit feedback input accuracy v fb 1 . 1 v output 1 . 091 1 . 11 . 109 v 1 . 6 v output 1 . 587 1 . 61 . 613 v 1 . 85 v output 1 . 835 1 . 85 1 . 865 v l i ne regulat i on v fb vcc = 10 v to 14 v 0 . 01 % input b i as current i fb 550 na crowbar tr i p po i nt v crowbar % of nom i nal output 115 120 125 % crowbar reset po i nt % of nom i nal output 40 50 60 % crowbar response t i me t crowbar overvoltage to pwm go i ng low 400 ns reference output voltage v ref 2 . 952 3 . 00 3 . 048 v output current i ref 300 a vid inputs input low voltage v il(vid) 0 . 8v input h i gh voltage v ih(vid) 2 . 0v input current i vid vid(x) = 0 v 70 90 a pull-up res i stance r vid 33 43 k internal pull-up voltage 2 . 73 . 03 . 3v oscillator max i mum frequency 2 f ct(max) 4000 khz frequency var i at i on f ct t a = 25 c, ct = 150 pf 475 575 675 khz t a = 25 c, ct = 68 pf 850 1000 1250 khz t a = 25 c, ct = 47 pf 1100 1300 1500 khz ct charge current i ct t a = 25 c, v fb i n regulat i on 260 300 340 a t a = 25 c, v fb = 0 v 40 65 80 a error amplifier output res i stance r o(err) 1m transconductance g m(err) 2 . 02 . 22 . 45 mmho output current i o(err) fb = 0 v 575 a max i mum output voltage v comp(max) fb forced to v out C 3% 3 . 0v output d i sable threshold v comp(off) 800 875 mv C3 db bandw i dth bw err comp = open 500 khz current sense threshold voltage v cs(th) cs+ = vcc, 143 158 173 mv fb forced to v out C 3% fb
750 mv 80 92 108 mv 0 . 8 v
share
1 v 0 5 mv input b i as current i cs+ , i csC cs+ = csC = vcc 1 5 a response t i me t cs cs+ C (csC) 173 mv 50 ns to pwm go i ng low current sharing output source current 2 ma output s i nk current 300 400 a max i mum output voltage v share(max) fb forced to v out C 3% 3 . 0v power good comparator undervoltage threshold v pwrgd(uv) percent of nom i nal output 75 80 85 % overvoltage threshold v pwrgd(ov) percent of nom i nal output 115 120 125 % output voltage low v ol(pwrgd) i pwrgd(sink) = 1 ma 375 525 mv response t i me 250 ns pwm outputs output voltage low v ol(pwm) i pwm(sink) = 400 a 100 500 mv output voltage h i gh v oh(pwm) i pwm(source) = 400 a4 . 05 . 0v duty cycle l i m i t per phase 2 dc 25 % rev. 1 | page 2 of 15 | www.onsemi.com rev. 2 | page 2 of 15 | www.onsemi.com
rev. 0 C3C ADP3164 parameter symbol conditions min typ max unit supply dc supply current normal mode i cc 3 . 75 5 . 5ma no cpu mode i cc(no cpu) vid4 C vid0 = open 3 . 55 . 5ma uvlo mode i cc(uvlo) vcc
v uvlo , vcc r i s i ng 350 500 a uvlo threshold voltage v uvlo 5 . 96 . 46 . 9v uvlo hysteres i s 0 . 50 . 81 . 0v notes 1 all l i m i ts at temperature extremes are guaranteed v i a correlat i on us i ng standard stat i st i cal qual i ty control (sqc) . 2 guaranteed by des i gn, not tested i n product i on . spec i f i cat i ons sub j ect to change w i thout not i ce . absolute maximum ratings * vcc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C0 . 3 v to +15 v cs+, csC . . . . . . . . . . . . . . . . . . . . . . C0 . 3 v to vcc +0 . 3 v all other inputs and outputs . . . . . . . . . . . . C0 . 3 v to +10 v operat i ng amb i ent temperature range . . . . . . . 0 c to 70 c operat i ng junct i on temperature . . . . . . . . . . . . . . . . . . 125 c storage temperature range . . . . . . . . . . . . C65 c to +150 c ja . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 c/w lead temperature (solder i ng, 10 sec) . . . . . . . . . . . . . 300 c vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * th i s i s a stress rat i ng only; operat i on beyond these l i m i ts can cause the dev i ce to be permanently damaged . unless otherw i se spec i ?ed, all voltages are referenced to pgnd . ordering guide model temperature range package description package option ADP3164jru 0 c to 70 cth i n shr i nk small outl i ne ru-20 (tssop-20) pin configuration ru-20 vid4 vid3 vid2 vid1 vid0 share comp gnd fb ct vcc ref pwm1 pwm2 pwm3 pwm4 pgnd csC cs+ pwrgd 3 1 4 5 18 17 16 2 20 19 6 10 7 8 9 11 14 13 12 15 ADP3164 top view (not to scale) warning! esd sensitive device caution esd (electrostat i c d i scharge) sens i t i ve dev i ce . electrostat i c charges as h i gh as 4000 v read i ly accumulate on the human body and test equ i pment and can d i scharge w i thout detect i on . although the ADP3164 features propr i etary esd protect i on c i rcu i try, permanent damage may occur on dev i ces sub j ected to h i gh-energy electrostat i c d i scharges . therefore, proper esd precaut i ons are recommended to avo i d performance degradat i on or loss of funct i onal i ty . rev. 1 | page 3 of 15 | www.onsemi.com rev. 2 | page 3 of 15 | www.onsemi.com
rev. 0 ADP3164 C4C pin function descriptions pin mnemonic function 1C5 vid4 C voltage ident i f i cat i on dac inputs . these p i ns are pulled up to an i nternal 3 v reference, prov i d i ng a vid0 log i c 1 i f left open . the dac output programs the fb regulat i on voltage from 1 . 1 v to 1 . 85 v . leav i ng all f i ve dac i nputs open results i n the ADP3164 go i ng i nto a no cpu mode, shutt i ng off i ts pwm outputs . 6 share current shar i ng output . th i s p i n i s connected to the share p i ns of other ADP3164s i n mult i ple vrm systems to ensure proper current shar i ng between the converters . the voltage at th i s output programs the output current control level between cs+ and csC . 7 comp error ampl i f i er output and compensat i on po i nt . 8 gnd ground . fb, ref, and the vid dac of the ADP3164 are referenced to th i s ground . th i s i s a low current ground that can also be used as a return for the fb p i n i n remote voltage sens i ng appl i cat i ons . 9 fb feedback input . error ampl i f i er i nput for remote sens i ng of the output voltage . 10 ct external capac i tor ct connect i on to ground sets the frequency of the dev i ce . 11 pwrgd open dra i n output that s i gnals when the output voltage i s outs i de of the proper operat i ng range or when a phase i s not supply i ng current even i f the output voltage i s i n spec i f i cat i on . 12 cs+ current sense pos i t i ve node . pos i t i ve i nput for the current comparator . the output current i s sensed as a voltage at th i s p i n w i th respect to csC . 13 csC current sense negat i ve node . negat i ve i nput for the current comparator . 14 pgnd power ground . all i nternal b i as i ng and log i c output s i gnals of the ADP3164 are referenced to th i s ground . 15 pwm4 log i c-level output for the phase 4 dr i ver . 16 pwm3 log i c-level output for the phase 3 dr i ver . 17 pwm2 log i c-level output for the phase 2 dr i ver . 18 pwm1 log i c-level output for the phase 1 dr i ver . 19 ref 3 . 0 v reference output . 20 vcc supply voltage for the ADP3164 . 5-bit code vid4 vid3 vid2 vid1 vid0 share comp gnd fb ct vcc ref pwm1 pwm2 pwm3 pwm4 pgnd csC cs+ pwrgd 3 1 4 5 18 17 16 2 20 19 6 7 8 9 11 14 13 12 15 ADP3164 12v 100 100nf 1 f 100nf ad820 v fb + 20k 10 1 . 2v figure 1. closed-loop output voltage accuracy test circuit rev. 1 | page 4 of 15 | www.onsemi.com rev. 2 | page 4 of 15 | www.onsemi.com
rev. 0 C5C typ i cal performance character i st i csCADP3164 ct capacitance C pf 10 0 . 1 0 100 50 frequency C mhz 1 150 250 200 300 tpc 1. oscillator frequency vs. timing capacitor (ct) oscillator frequency C khz 4 . 5 4 . 0 0 1000 500 supply current C ma 4 . 4 1500 2500 2000 3000 4 . 3 4 . 2 4 . 1 tpc 2. supply current vs. oscillator frequency output accuracy C % of nominal 25 0 C0 . 5 number of parts C % 20 00 . 5 15 10 5 t a = 25 c v out = 1 . 6v tpc 3. output accuracy distribution rev. 1 | page 5 of 15 | www.onsemi.com rev. 2 | page 5 of 15 | www.onsemi.com
rev. 0 ADP3164 C6C theory of operation the ADP3164 comb i nes a current-mode, f i xed frequency pwm controller w i th mult i phase log i c outputs for use i n a 4-phase syn- chronous buck power converter . mult i phase operat i on i s i mportant for sw i tch i ng the h i gh currents requ i red by h i gh performance m i croprocessors . handl i ng the h i gh current i n a s i ngle-phase converter would place unreasonable requ i rements on the power components such as i nductor w i re s i ze and mosfet on- res i stance and thermal d i ss i pat i on . the ADP3164s h i gh s i de current sens i ng topology ensures that the load currents are bal- anced i n each phase, such that no s i ngle phase has to carry more than i ts share of the power . an add i t i onal benef i t of h i gh s i de current sens i ng over output current sens i ng i s that the average current through the sense res i stor i s reduced by the duty cycle of the converter allow i ng the use of a lower power, lower cost res i stor . the outputs of the ADP3164 are log i c dr i vers only and are not i ntended to d i rectly dr i ve external power mosfets . instead, the ADP3164 should be pa i red w i th dr i vers such as the adp3413 . table i. output voltage vs. vid code vid4 vid3 vid2 vid1 vid0 v out(nom) 11111no cpu 111101 . 100 v 111011 . 125 v 111001 . 150 v 110111 . 175 v 110101 . 200 v 110011 . 225 v 110001 . 250 v 101111 . 275 v 101101 . 300 v 101011 . 325 v 101001 . 350 v 100111 . 375 v 100101 . 400 v 100011 . 425 v 100001 . 450 v 011111 . 475 v 011101 . 500 v 011011 . 525 v 011001 . 550 v 010111 . 575 v 010101 . 600 v 010011 . 625 v 010001 . 650 v 001111 . 675 v 001101 . 700 v 001011 . 725 v 001001 . 750 v 000111 . 775 v 000101 . 800 v 000011 . 825 v 000001 . 850 v the frequency of the ADP3164 i s set by an external capac i tor connected to the ct p i n . the error ampl i f i er and current sense comparator control the duty cycle of the pwm outputs to ma i n- ta i n regulat i on . the max i mum duty cycle per phase i s i nherently l i m i ted to 25% . wh i le one phase i s on, all other phases rema i n off . in no case can more than one output be h i gh at any t i me . output voltage sensing the output voltage i s sensed at the fb p i n allow i ng for remote sens i ng . to ma i nta i n the accuracy of the remote sens i ng, the gnd p i n should also be connected close to the load . a voltage error ampl i f i er (g m ) ampl i f i es the d i fference between the output voltage and a programmable reference voltage . the reference voltage i s programmed between 1 . 1 v and 1 . 85 v by an i nternal 5-b i t dac, wh i ch reads the code at the voltage i dent i f i cat i on (vid) p i ns . (refer to table i for the output voltage versus vid p i n code i nformat i on . ) active voltage positioning the ADP3164 uses analog dev i ces opt i mal pos i t i on i ng tech- nology (adopt), a un i que supplemental regulat i on techn i que that uses act i ve voltage pos i t i on i ng and prov i des opt i mal com- pensat i on for load trans i ents . when i mplemented, adopt ad j usts the output voltage as a funct i on of the load current, so that i t i s always opt i mally pos i t i oned for a load trans i ent . standard (pass i ve) voltage pos i t i on i ng has poor dynam i c performance, render i ng i t i neffect i ve under the str i ngent repet i t i ve trans i ent cond i t i ons requ i red by h i gh performance processors . adopt, however, prov i des a bandw i dth for trans i ent response that i s l i m i ted only by paras i t i c output i nductance . th i s y i elds opt i mal load tran- s i ent response w i th the m i n i mum number of output capac i tors . reference output a 3 . 0 v reference i s ava i lable on the ADP3164 . th i s reference i s normally used to accurately set the voltage pos i t i on i ng us i ng a res i stor d i v i der to the comp p i n . in add i t i on, the reference can be used for other funct i ons such as generat i ng a regulated voltage w i th an external ampl i f i er . the reference i s bypassed w i th a 1 nf capac i tor to ground . it i s not i ntended to dr i ve larger capac i t i ve loads, and i t should not be used to prov i de more than 300 a of output current . cycle-by-cycle operation dur i ng normal operat i on (when the output voltage i s regulated), the voltage-error ampl i f i er and the current comparator are the ma i n control elements . the free runn i ng osc i llator ramps be tween 0 v and 3 v . when the voltage on the ct p i n reaches 3 v, the osc i llator sets the dr i ver log i c, wh i ch sets pwm1 h i gh . dur i ng the on t i me of phase 1, the dr i ver ic turns on the phase 1 h i gh s i de mosfet . the cs+ and csC p i ns mon i tor the current through the sense res i stor that feeds all of the h i gh s i de mosfets . when the voltage between the two p i ns exceeds the threshold level, the dr i ver log i c i s reset and the pwm1 output goes low . th i s s i gnals the dr i ver ic to turn off the phase 1 h i gh s i de mosfet and turn on the phase 1 low s i de mosfet . on the next cycle of the osc i llator, the dr i ver log i c toggles and sets pwm2 h i gh . the current i s then steered through the second phase . th i s cycle cont i nues for each of the pwm outputs . rev. 1 | page 6 of 15 | www.onsemi.com rev. 2 | page 6 of 15 | www.onsemi.com
rev. 0 ADP3164 C7C on each of the follow i ng cycles of the osc i llator, the outputs cycle be tween each of the act i ve pwm outputs . in each case, the current comparator resets the pwm output low when the vt1 i s reached . the current of each phase i s sensed w i th the same res i stor and the same comparator, so the current i s i nherently balanced . as the load current i ncreases, the output voltage starts to decrease . th i s causes an i ncrease i n the output of the voltage error ampl i f i er (g m ), wh i ch i n turn leads to an i ncrease i n the current comparator threshold vt1, thus track i ng the load current . active current sharing the ADP3164 ensures current balance i n all the act i ve phases by sens i ng the current through a s i ngle sense res i stor . dur i ng one phases on t i me, the current through the respect i ve h i gh s i de mosfet and i nductor i s measured through the sense res i stor . when the comparator threshold i s reached, the h i gh s i de mosfet turns off . on the next cycle the ADP3164 sw i tches to the next phase . the current i s measured w i th the same sense res i stor and the same i nternal comparator, ensur i ng accurate match i ng . th i s scheme i s i mmune to i mbalances i n the mosfets r ds(on) and i nductor paras i t i c res i stance . if for some reason one of the phases has a short c i rcu i t fa i lure, the other phases w i ll st i ll be l i m i ted to the i r max i mum output current (one over the total number phases t i mes the total short c i rcu i t current l i m i t) . if th i s i s not suff i c i ent to supply the load, the output voltage w i ll droop and cause the pwrgd output to s i gnal that the output voltage has fallen out of i ts spec i f i ed range . if one of the phases has an open c i rcu i t fa i lure, the ADP3164 w i ll detect the open phase and s i gnal the problem v i a the pwrgd p i n (see power good mon i tor i ng sect i on) . current sharing in multi-vrm applications the ADP3164 i ncludes a share p i n to allow mult i ple vrms to accurately share load current . in mult i ple vrm appl i cat i ons, the share p i ns should be connected together . th i s p i n i s a low i mpedance buffered output of the comp p i n voltage . the output of the buffer i s i nternally connected to set the threshold of the current sense comparator . the buffer has a 400 a s i nk current, and a 2 ma sourc i ng capab i l i ty . the strong pull-up allows one vrm to control the current threshold set po i nt for all ADP3164s connected together . the ADP3164s h i gh accu- racy current set threshold ensures good current balance between vrms . also, the low i mpedance of the buffer m i n i m i zes no i se p i ckup on th i s trace wh i ch i s routed to mult i ple vrms . th i s c i rcu i t operates i n add i t i on to the act i ve current shar i ng between phases of each vrm descr i bed above . short circuit protection the ADP3164 has mult i ple levels of short c i rcu i t protect i on to ensure fa i l-safe operat i on . the sense res i stor and the max i mum current sense threshold voltage g i ven i n the spec i f i cat i ons set the peak current l i m i t . when the load current exceeds the current l i m i t, the excess current d i scharges the output capac i tor . when the output volt- age i s below the foldback threshold, v fb(low) , the max i mum del i verable output current i s cut by reduc i ng the current sense threshold from the current l i m i t threshold, v cs(cl) , to the fold- back threshold, v cs(fold) . along w i th the result i ng current foldback, the osc i llator frequency i s reduced by a factor of f i ve when the output i s 0 v . th i s further reduces the average curre n i n short c i rcu i t . power good monitoring the power good comparator mon i tors the output voltage of th e supply v i a the fb p i n . the pwrgd p i n i s an open dra i n outp u whose h i gh level (when connected to a pull-up res i stor) i nd i cates that the output voltage i s w i th i n the spec i f i ed range of the nom i . pwrgd w i ll g o low i f the output i s outs i de th i s range . short c i rcu i ts i n a vrm power path are relat i vely easy to detec t i n appl i cat i ons where mult i ple vrms are connected to a com- mon power plane . vrm power tra i n open fa i lures are not as eas i ly spotted, s i nce the other vrms may be able to supply enough total current to keep the output voltage w i th i n the power good voltage spec i f i cat i on even when one vrm i s not funct i on i ng . the ADP3164 addresses th i s problem by mon i tor - i ng both the output voltage and the sw i tch current to determ i n e the state of the pwrgd output . the output voltage port i on of the power good mon i tor dom i - nates; as long as the output voltage i s outs i de the spec i f i ed w i ndow, pwrgd w i ll rema i n low . if the output voltage i s w i th i n spec i f i cat i on, a second c i rcu i t checks to make sure that current i s be i ng del i vered to the output by each phase . if no current i s detected i n a phase for three consecut i ve cycles, i t i s assumed that an open c i rcu i t ex i sts somewhere i n the power path, and pwrgd w i ll be pulled low . output crowbar the ADP3164 i ncludes a crowbar comparator that senses whe n the output voltage r i ses h i gher than the spec i f i ed tr i p threshold , v crowbar . th i s comparator overr i des the control loop and sets both pwm outputs low . the dr i ver ics turn off the h i gh s i d e mosfets and turn on the low s i de mosfets, thus pull i ng the output down as the reversed current bu i lds up i n the i nduc - tors . if the output overvoltage i s due to a short of the h i gh s i de mosfet, th i s act i on w i ll current-l i m i t the i nput supply or blo w i ts fuse, protect i ng the m i croprocessor from destruct i on . th e crowbar comparator releases when the output drops below the spec i f i ed reset threshold, and the controller returns to normal operat i on i f the cause of the overvoltage fa i lure does not pers i st output disable the ADP3164 i ncludes an output d i sable funct i on that turns o f the control loop to br i ng the output voltage to 0 v . because an extra p i n i s not ava i lable, the d i sable feature i s accompl i shed b y pull i ng the comp p i n to ground . when the comp p i n drops below 0 . 8 v, the osc i llator stops and all pwm s i gnals are dr i ve n low . th i s funct i on does not place the part i n low current shut- down and the reference voltage i s st i ll ava i lable . the comp p i n should be pulled down w i th an open dra i n type of output capable of s i nk i ng at least 2 ma . rev. 1 | page 7 of 15 | www.onsemi.com rev. 2 | page 7 of 15 | www.onsemi.com
rev. 0 ADP3164 C8C in vcc bst drvh sw drvl pgnd u2 adp3414 nc 7 6 5 1 2 3 4 8 vid4 vid3 vid2 vid1 vid0 share comp gnd fb ct vcc ref pwm1 pwm2 pwm3 pwm4 pgnd csC cs+ pwrgd 3 1 4 5 18 17 16 2 20 19 6 10 7 8 9 11 14 13 12 15 ADP3164 1 . 5k r z 1 . 2nf c oc in vcc bst drvh sw drvl pgnd u3 adp3414 nc 7 6 5 1 2 3 4 8 in vcc bst drvh sw drvl pgnd u4 adp3414 nc 7 6 5 1 2 3 4 8 in vcc bst drvh sw drvl pgnd u5 adp3414 dly 7 6 5 1 2 3 4 8 l2 600nh q2 fdb7030l c14 15nf r8 2 l3 600nh q3 fdb7030l c17 15nf r9 2 l4 600nh q4 fdb7030l c20 15nf r10 2 l5 600nh q5 fdb7030l c23 15nf r11 2 + + r5 20 c7 10nf c8 1nf r b 10 . 5k c10 100pf c11 100pf 1k r3 26 . 7k r a u1 r4 10 c5 4 . 7 f + + + c1 c2 c3 v in rtn v in 12v l1 1 h 270 f/16v x 3 os-con sp series c13 4 . 7 f r6 2k r7 5m c12 100nf z1 zmm5263bct q1 fz649ta d1 mbr052lti c16 4 . 7 f d2 mbr052lti d3 mbr052lti d5 mbr052lti c19 4 . 7 f c22 4 . 7 f c15 100nf c18 100nf c21 100nf 820 f/4v x 13 os-con sp series 12m esr (each) c24 c37 v cc(core) 1 . 1v C 1 . 85v 80a v cc(core)rtn q6 fdb8030l q8 fdb8030l q9 fdb8030l q7 fdb8030l c6 4 . 7 f 10 f 2 mlcc nc = no connect figure 2. 80 a intel vrm 9.1-compliant cpu supply circuit rev. 1 | page 8 of 15 | www.onsemi.com rev. 2 | page 8 of 15 | www.onsemi.com
rev. 0 ADP3164 C9C application information the des i gn parameters for a typ i cal vrm 9 . 1-compl i ant cpu appl i cat i on are as follows: input voltage (v in ) = 12 v vid sett i ng voltage (v vid ) = 1 . 475 v nom i nal output voltage at no load (v onl ) = 1 . 4605 v nom i nal output voltage at 80 a load (v ofl ) = 1 . 3845 v stat i c output voltage drop based on a 0 . 95 m load l i ne (r out ) from no load to full load (v ) = v onl C v ofl = 1 . 4605 v C 1 . 3845 v = 76 mv max i mum output current (i o ) = 81 a number of phases (n) = 4 ct selectionchoosing the clock frequency the ADP3164 uses a f i xed-frequency control arch i tecture . the frequency i s set by an external t i m i ng capac i tor, ct . the clock frequency determ i nes the sw i tch i ng frequency, wh i ch relates d i rectly to sw i tch i ng losses and the s i zes of the i nductors and i nput and output capac i tors . a clock frequency of 800 khz sets the sw i tch i ng frequency of each phase, f sw , to 200 khz, wh i ch represents a pract i cal trade-off between the sw i tch i ng losses and the s i zes of the output f i lter components . to ach i eve an 800 khz osc i llator frequency, the requ i red t i m i ng capac i tor value i s 100 pf . for good frequency stab i l i ty and i n i t i al accuracy, i t i s recom- mended to use a capac i tor w i th low temperature coeff i c i ent and t i ght tolerance, e . g . , an mlc capac i tor w i th npo d i elec- tr i c and w i th 5% or less tolerance . inductance selection the cho i ce of i nductance determ i nes the r i pple current i n the i nductor . less i nductance leads to more r i pple current, wh i ch i ncreases the output r i pple voltage and the conduct i on losses i n the mosfets, but allows us i ng smaller-s i ze i nductors and, for a spec i f i ed peak-to-peak trans i ent dev i at i on, output capac i tors w i th less total capac i tance . conversely, a h i gher i nductance means lower r i pple current and reduced conduct i on losses, but requ i res larger-s i ze i nductors and more output capac i tance for the same peak-to-peak trans i ent dev i at i on . in a 4-phase con- verter, a pract i cal value for the peak-to-peak i nductor r i pple current i s under 50% of the dc current i n the same i nductor . a cho i ce of 50% for th i s part i cular des i gn example y i elds a total peak-to-peak output r i pple current of 8% of the total dc output current . the follow i ng equat i on shows the relat i onsh i p between the i nductance, osc i llator frequency, peak-to-peak r i pple current i n an i nductor and i nput and output voltages . l vv v vf i in out out in sw l ripple (C ) () (1) for 10 a peak-to-peak r i pple current, wh i ch i s 50% of the 20 a full-load dc current i n an i nductor, equat i on 1 y i elds an i nductance of: l vv v v khz a nh (C . ) . 12 1 475 1 475 12 800 4 10 646 a 600 nh i nductor can be used, wh i ch g i ves a calculated r i pple current of 10 . 8 a at no load . the i nductor should not saturate at the peak current of 26 a, and should be able to handle the sum of the power d i ss i pat i on caused by the average current of 20 a i n the w i nd i ng and the core loss . the output r i pple current i s smaller than the i nductor r i pple current due to the four phases part i ally cancel i ng . th i s can be calculated as follows: i nv v nv vlf i vv v v nh khz a o out in out in osc o (C ) . (C . ) . 4 1 475 12 4 1 475 12 600 800 625 ( 2 designing an inductor once the i nductance i s known, the next step i s e i ther to des i gn an i nductor or f i nd a standard i nductor that comes as close as poss i ble to meet i ng the overall des i gn goals . the f i rst dec i s i on i i gn i ng the i nductor i s to choose the core mater i al . there ar e several poss i b i l i t i es for prov i d i ng low core loss at h i gh frequenc i es . two examples are the powder cores (e . g . , kool-m ? from magnet i cs, inc . ) and the gapped soft ferr i te cores (e . g . , 3f3 or 3f4 from ph i l i ps) . low frequency powdered i ron cores should be avo i ded due to the i r h i gh core loss, espec i ally when the i nduc - tor value i s relat i vely low and the r i pple current i s h i gh . two ma i n core types can be used i n th i s appl i cat i on . open magnet i c loop types, such as beads, beads on leads, and rods and slugs, prov i de lower cost but do not have a focused mag- net i c f i eld i n the core . the rad i ated emi from the d i str i buted magnet i c f i eld may create problems w i th no i se i nterference i n the c i rcu i try surround i ng the i nductor . closed-loop types, suc h as pot cores, pq, u, and e cores, or toro i ds, cost more, but have much better emi/rfi performance . a good comprom i se between pr i ce and performance are cores w i th a toro i dal shape . there are many useful references for qu i ckly des i gn i ng a powe r i nductor . table ii g i ves some examples . table ii. magnetics design references magnet i c des i gner software intusoft (http://www .i ntusoft . com) des i gn i ng magnet i c components for h i gh-frequency dc-d c converters mclyman, kg magnet i cs isbn 1-883107-00-08 selecting a standard inductor the compan i es l i sted i n table iii can prov i de des i gn consulta- t i on and del i ver power i nductors opt i m i zed for h i gh power appl i cat i ons upon request . table iii. power inductor manufacturers co i lcraft (847)639-6400 http://www . co i lcraft . com co i ltron i cs (561)752-5000 http://www . co i ltron i cs . com sum i da electr i c company (408)982-9660 http://www . sum i da . com rev. 1 | page 9 of 15 | www.onsemi.com rev. 2 | page 9 of 15 | www.onsemi.com
rev. 0 ADP3164 C10C r sense the value of r sense i s based on the max i mum requ i red output current . the current comparator of the ADP3164 has a m i n i - mum current l i m i t threshold of 143 mv . note that the 143 mv value cannot be used for the max i mum spec i f i ed nom i nal cur- rent, as headroom i s needed for r i pple current and tolerances . the current comparator threshold sets the peak of the i nductor current y i eld i ng a max i mum output current, i o , wh i ch equals tw i ce the peak i nductor current value less half of the peak-to- peak i nductor r i pple current . from th i s, the max i mum value of r sense i s calculated as: r v i n i mv aa m sense cscl min o l ripple
() () . . 2 143 80 4 10 8 2 56 (3) in th i s case, 5 m was chosen as the closest standard value . once r sense has been chosen, the output current at the po i nt where current l i m i t i s reached, i out(cl) , can be calculated us i ng the max i mum current sense threshold of 173 mv: in v r ni i mv m a a out cl cscl max sense l ripple out cl () () ( ) () . . 2 4 173 5 4108 2 116 8 (4) at output voltages below 750 mv, the current sense threshold i s reduced to 108 mv, and the r i pple current i s negl i g i ble . there- fore, at dead short the output current i s reduced to: in v r mv m a out sc cs sc sense () () . 4 108 5 86 4 (5) to safely carry the current under max i mum load cond i t i ons, the sense res i stor must have a power rat i ng of at least: pi r r sense rms sense sense () 2 (6) where: i i n v v sense rms o out in () 2 2 (7) in th i s formula, n i s the number of phases, and i s the con- verter eff i c i ency, i n th i s case assumed to be 85% . comb i n i ng equat i ons 6 and 7 y i elds: p av v mw r sense 80 4 1 475 085 12 512 2 . . . output resistance th i s des i gn requ i res that the regulator output voltage measured at the cpu drop when the output current i ncreases . the spec i - f i ed voltage drop corresponds to a dc output res i stance of: r vv i vv a m out onl ofl o 1 4605 1 3845 80 095 .. . (8) the requ i red dc output res i stance can be ach i eved by term i nat i ng the g m ampl i f i er w i th a res i stor . the value of the total term i na- t i on res i stance that w i ll y i eld the correct dc output res i stance: r nr ng r m mmho m k t i sense m out 12 5 5 422 095 748 . .. . (9) where n i i s the d i v i s i on rat i o from the output voltage s i gnal of the g m ampl i f i er to the pwm comparator cmp1, g m i s the transconductance of the g m ampl i f i er i tself, and n i s the number of phases . output offset intels vrm 9 . 1 spec i f i cat i on requ i res that at no load the nom i nal output voltage of the regulator be offset to a lower value than the nom i nal voltage correspond i ng to the vid code to make sure that c i rcu i t tolerances never cause the output voltage to exceed the vid value . the offset i s i ntroduced by real i z i ng the total term i na- t i on res i stance of the g m ampl i f i er w i th a d i v i der connected between the ref p i n and ground . the res i st i ve d i v i der i ntroduces an offset to the output of the g m ampl i f i er that, when reflected back through the ga i n of the g m stage, accurately pos i t i ons the output voltage near i ts allowed max i mum at l i ght load . furthermore, the output of the g m ampl i f i er sets the current sense threshold voltage . at no load, the current sense threshold i s i ncreased by the peak of the r i pple current i n the i nductor and reduced by the delay between sens i ng when the current threshold has been reached and when the h i gh s i de mosfet actually turns off . these two factors are comb i ned w i th the i nherent voltage (v gnl0 ), at the output of the g m ampl i f i er that commands a current sense threshold of 0 mv: vv irn vv l nt r n vv am v v nh ns m v gnl gnl l ripple sense i in out d sense i gnl 0 2 1 10 8 5 12 5 2 12 1 475 600 4 60 5 12 5 1 074 () ... .. (10) the d i v i der res i stors (r a for the upper and r b for the lower) can now be calculated, assum i ng that the i nternal res i stance of the g m ampl i f i er (r ogm ) i s 1 m : r v vv r gv v r v vv k mmho v v k b ref ref gnl t m onl vid b () . . . ( .. ) . 3 3 1 074 748 2 2 1 4605 1 475 10 37 (11) choos i ng the nearest 1% res i stor value g i ves r b = 10 . 5k . f i nally, r a i s calculated: r rr r k m k k a t ogm b 1 111 1 1 748 1 1 1 10 5 26 7 .. . (12) choos i ng the nearest 1% res i stor value g i ves r a = 26 . 7k . rev. 1 | page 10 of 15 | www.onsemi.com rev. 2 | page 10 of 15 | www.onsemi.com
rev. 0 ADP3164 C11C c out selection the requ i red equ i valent ser i es res i stance (esr) and capac i tance dr i ve the select i on of the type and quant i ty of the output capac i - tors . the esr must be less than or equal to the spec i f i ed output res i stance (r out ), i n th i s case 0 . 95 m . the capac i tance must be large enough that the voltage across the capac i tors, wh i ch i s the sum of the res i st i ve and capac i t i ve voltage dev i at i ons, does not dev i ate beyond the i n i t i al res i st i ve step wh i le the i nductor current ramps up or down to the value correspond i ng to the new load current . one can, for example, use th i rteen sp-type os-con capac i - tors from sanyo, w i th 820 f capac i tance, a 4 v voltage rat i ng, and 12 m esr . the ten capac i tors have a max i mum total esr of 0 . 92 m when connected i n parallel . as long as the capac i tance of the output capac i tor bank i s above a cr i t i cal value and the regulat i ng loop i s compensated w i th analog dev i ces propr i etary compensat i on techn i que (adopt), the actual capac i tance value has no i nfluence on the peak-to- peak dev i at i on of the output voltage to a full step change i n the load current . the cr i t i cal capac i tance can be calculated as follows: c i rv l n a mv nh mf out crit o out out () .. . 80 0 95 1 475 600 4 856 (13) the cr i t i cal capac i tance l i m i t for th i s c i rcu i t i s 8 . 56 mf, wh i le the actual capac i tance of the th i rteen os-con capac i tors i s 13 820 f = 10 . 66 mf . in th i s case, the capac i tance i s safely above the cr i t i cal value . mult i layer ceram i c capac i tors are also requ i red for h i gh-frequency decoupl i ng of the processor . the exact number of these mlc capac i tors i s a funct i on of the board layout space and paras i t i cs . typ i cal des i gns use twenty to th i rty 10 f mlc capac i tors located as close to the processor power p i ns as i s pract i cal . feedback loop compensation design for adopt opt i m i zed compensat i on of the ADP3164 allows the best pos- s i ble conta i nment of the peak-to-peak output voltage dev i at i on . any pract i cal sw i tch i ng power converter i s i nherently l i m i ted by the i nductor i n i ts output current slew rate to a value much less than the slew rate of the load . therefore, any sudden change of load current w i ll i n i t i ally flow through the output capac i tors, and assum i ng that the capac i tance of the output capac i tor i s larger than the cr i t i cal value def i ned by equat i on 13, th i s w i ll produce a peak output voltage dev i at i on equal to the esr of the output capac i tor t i mes the load current change . the opt i mal i mplementat i on of voltage pos i t i on i ng, adopt, w i ll create an output i mpedance of the power converter that i s ent i rely res i st i ve over the w i dest poss i ble frequency range, i nclud- i ng dc, and equal to the max i mum acceptable esr of the output capac i tor array . w i th the res i st i ve output i mpedance, the output voltage w i ll droop i n proport i on w i th the load current at any load current slew rate; th i s ensures the opt i mal pos i t i on i ng and allows the m i n i m i zat i on of the output capac i tor bank . w i th an i deal current-mode-controlled converter, where the average i nductor current would respond w i thout delay to the command s i gnal, the res i st i ve output i mpedance could be ach i eved by hav i ng a s i ngle-pole roll-off of the voltage ga i n of the voltage-error ampl i f i er . the pole frequency must co i nc i de w i th the esr zero of the output capac i tor bank . the adp316 4 uses constant frequency current-mode control, wh i ch i s known to have a non i deal, frequency-dependent command s i gnal to i nductor current transfer funct i on . the frequency dependence man i fests i n the form of a pa i r of complex con j ugate poles at one-half of the sw i tch i ng frequency . a purely res i st i ve output i mpedance could be ach i eved by cancel i ng the complex con j ugate poles w i th zeros at the same complex frequenc i es and add i ng a th i rd pole equal to the esr zero of the output capac i tor . such compensat i ng network would be qu i te compl i cated . fortunately, i i ce i t i s suff i c i ent to cancel the pa i r of complex con j ugate poles w i th a s i ngle real zero placed at one-half of the sw i tch i ng frequency . although the end result i s not a perfectly res i st i ve output i mpedance, the rema i n i ng frequency dependence cause s only a small percentage of dev i at i on from the i deal res i st i ve response . the s i ngle-pole and s i ngle-zero compensat i on can eas i l y be i mplemented by term i nat i ng the g m error ampl i f i er w i th the parallel comb i nat i on of a res i stor (r t ) and a ser i es rc networ k the value of the term i nat i ng res i stor r t was prev i ously deter- m i ned; the capac i tance and res i stance of the ser i es rc networ k are calculated as follows: c cr r n fr c mf m k khz k nf oc out out t osc t oc 10 7 0 92 748 4 800 7 48 11 .. .. . (1 4 the nearest standard value of c oc i s 1 nf . the res i stance of th zero-sett i ng res i stor i n ser i es w i th the compensat i ng capac i tor i s r n f c khz nf k z osc oc 4 800 1 159 . (1 5 the nearest standard 5% res i stor value i s 1 . 5 k . note that th i s res i stor i s only requ i red when c out approaches c crit (w i th i n 25% or less) . in th i s example, c out i s approach i ng c crit , s o r z should be i ncluded . power mosfets in th i s example, e i ght n-channel power mosfets must be used ; four as the ma i n (control) sw i tches, and the rema i n i ng four as the synchronous rect i f i er sw i tches . the ma i n select i on parameter s for the power mosfets are v gs(th) , q g and r ds(on) . the m i n i mum gate dr i ve voltage (the supply voltage to the adp3414) d i ctates whether standard threshold or log i c-level threshold mosfets must be used . s i nce v gate <8 v, log i c-level thresh - old mosfets (v gs(th) < 2 . 5 v) are strongly recommended . rev. 1 | page 11 of 15 | www.onsemi.com rev. 2 | page 11 of 15 | www.onsemi.com
rev. 0 ADP3164 C12C the max i mum output current i o determ i nes the r ds(on) requ i re- ment for the power mosfets . when the ADP3164 i s operat i ng i n cont i nuous mode, the s i mpl i fy i ng assumpt i on can be made that i n each phase one of the two mosfets i s always conduct i ng the average i nductor current . for v in =12 v and v out = 1 . 475 v, the duty rat i o of the h i gh-s i de mosfet i s: d v v v v hsf out in 1 475 12 12 3 . . % (16) the duty rat i o of the low-s i de (synchronous rect i f i er) mosfet i s: dd lsf max hsf max () () . % 1877 (17) the max i mum rms current of the h i gh-s i de mosfet dur i ng normal operat i on i s: i i n d i i aa a a hsf max o hsf l ripple o () () . . . 1 3 80 4 0 123 1 10 8 380 702 2 2 2 2 (18) the max i mum rms current of the low-s i de mosfet dur i ng normal operat i on i s: ii d d aa lsf max hfs m ax lsf hsf () ( ) . . . . 702 0 877 0 123 18 75 (19) the r ds(on) for each mosfet can be der i ved from the allowable d i ss i pat i on . if 10% of the max i mum output power i s allowed for mosfet d i ss i pat i on, the total d i ss i pat i on i n the e i ght mosfets of the 4-phase converter w i ll be: pvi pvaw fet total min o fet total () () . .. . 01 0 1 1 3845 80 11 08 (20) allocat i ng half of the total d i ss i pat i on for the four h i gh-s i de mosfets and half for the four low-s i de mosfets, and assum i ng that the res i st i ve and sw i tch i ng losses of the h i gh-s i de mosfets are equal, the requ i red max i mum mosfet res i s- tances w i ll be: r p ni r w a m ds on hsf fet total hsf max ds on hsf () () () () . . 4 11 08 44702 14 2 2 (21) and: r p ni r w a m ds on lsf fet total lsf max ds on lsf () () () () . . . 2 11 08 2 4 18 75 394 2 2 (22) note that there i s a trade-off between converter eff i c i ency and cost . larger mosfets reduce the conduct i on losses and allow h i gher eff i c i ency, but i ncrease the system cost . a fa i rch i ld fdb7030l (r ds(on) = 7 m nom i nal, 10 m worst-case) for the h i gh-s i de and a fa i rch i ld fdb8030l (r ds(on) = 3 . 1 m nom i nal, 5 . 6 m worst-case) for the low-s i de are good cho i ces . the h i gh-s i de mosfet d i ss i pat i on i s: pr i vi qf i vq f pm a v a nc khz a v nc khz w hsf ds on hsf hsf max in l pk g sw g in rr sw hsf () ( ) () . . 2 2 2 10 7 02 12 26 35 200 21 12 150 200 1 95 (23) where the f i rst term i s the conduct i on loss of the mosfet, the second term represents the turn-off loss of the mosfet and the th i rd term represents the turn-on loss due to the stored charge i n the body d i ode of the low-s i de mosfet . in the sec- ond term, q g i s the gate charge to be removed from the gate for turn-off and i g i s the gate turn-off current . from the data sheet, for the fdb7030l the value of q g i s about 35 nc and the peak gate dr i ve current prov i ded by the adp3414 i s about 1 a . in the th i rd term, q rr , i s the charge stored i n the body d i ode of the low-s i de mosfet at the valley of the i nductor current . the data sheet of the fdb8030l does not g i ve that i nformat i on, so an est i mated value of 150 nc i s used . th i s est i mate i s based on i nformat i on found on data sheets of s i m i lar dev i ces . in both terms, f sw i s the actual sw i tch i ng frequency of the mosfets, or 200 khz . i l(pk) i s the peak current i n the i nductor, or 26 a . the worst-case low-s i de mosfet d i ss i pat i on i s: pr i pm aw lsf ds on lsf lsf max lsf () ( ) ... 2 2 5 6 18 75 1 97 (24) note that there are no sw i tch i ng losses i n the low-s i de mosfet . c in selection and input current di/dt reduction in cont i nuous i nductor-current mode, the source current of the h i gh-s i de mosfet i s approx i mately a square wave w i th a duty rat i o equal to v out /v in and an ampl i tude of one-half of the max i mum output current . to prevent large voltage trans i ents, a low esr i nput capac i tor s i zed for the max i mum rms current must be used . the max i mum rms capac i tor current i s g i ven by: i i n nd nd i a a c rms o hsf hsf c rms () () C( ) . ( . ) 2 2 80 4 4 0 123 4 0 123 10 (25) note that the capac i tor manufacturers r i pple current rat i ngs are often based on only 2000 hours of l i fe . th i s makes i t adv i sable to further derate the capac i tor, or to choose a capac i tor rated at a h i gher temperature than requ i red . several capac i tors may be placed i n parallel to meet s i ze or he i ght requ i rements i n the des i gn . in th i s example, the i nput capac i tor bank i s formed by three 270 f, 16 v os-con capac i tors w i th a r i pple current rat i ng of 4 . 4 a each . rev. 1 | page 12 of 15 | www.onsemi.com rev. 2 | page 12 of 15 | www.onsemi.com
rev. 0 ADP3164 C13C the r i pple voltage across the three paralleled capac i tors i s: v i n esr n d nc f am f khz mv c ripple oc c hsf cinsw () . 80 4 18 3 0 123 3 270 200 135 (26) mult i layer ceram i c i nput capac i tors are also requ i red . these capac i tors should be placed between the input s i de of the cur- rent sense res i stor and the sources of the low-s i de synchronous mosfets . these capac i tors decouple the h i gh-frequency lead- i ng edge current sp i ke that suppl i es the reverse recovery charge of the low-s i de mosfets body d i ode . the exact number requ i red i s a funct i on of the board layout . typ i cal des i gns w i ll use two 10 f mlc capac i tors . to reduce the i nput-current d i / dt to below the recommended max i mum of 0 . 1 a/ s, an add i - t i onal small i nductor (l > 1 h @ 15 a) should be i nserted between the converter and the supply bus . that i nductor also acts as a f i lter between the converter and the pr i mary power source . layout and component placement guidelines the follow i ng gu i del i nes are recommended for opt i mal perfor- mance of a sw i tch i ng regulator i n a pc system . general recommendations 1 . for good results, at least a four-layer pcb i s recomm ended . th i s should allow the needed versat i l i ty for control c i rcu i try i nterconnect i ons w i th opt i mal placement, a s i gnal ground plane, power planes for both power ground and the i nput power (e . g . , 12 v), and w i de i nterconnect i on traces i n the rest of the power del i very current paths . keep i n m i nd that each square un i t of 1 ounce copper trace has a res i stance of ~0 . 53 m at room temperature . 2 . whenever h i gh currents must be routed between pcb layers, v i as should be used l i berally to create several parallel current paths so that the res i stance and i nductance i ntro- duced by these current paths i s m i n i m i zed and the v i a current rat i ng i s not exceeded . 3 . if cr i t i cal s i gnal l i nes ( i nclud i ng the voltage and current sense l i nes of the ADP3164) must cross through power c i rcu i try, i t i s best i f a s i gnal ground plane can be i nter- posed between those s i gnal l i nes and the traces of the power c i rcu i try . th i s serves as a sh i eld to m i n i m i ze no i se i n j ect i on i nto the s i gnals at the expense of mak i ng s i gnal ground a b i t no i s i er . 4 . the power ground plane should not extend under s i gnal components, i nclud i ng the ADP3164 i tself . if necessary, follow the preced i ng gu i del i ne to use the s i gnal ground plane as a sh i eld between the power ground plane and the s i gnal c i rcu i try . 5 . the gnd p i n of the ADP3164 should be connected f i rst to the t i m i ng capac i tor (on the ct p i n), and then i nto the s i gnal ground plane . in cases where no s i gnal ground plane can be used, short i nterconnect i ons to other s i gnal ground c i rcu i try i n the power converter should be used . 6 . the output capac i tors of the power converter should be connected to the s i gnal ground plane even though power current flows i n the ground of these capac i tors . for th i s reason, i t i s adv i sed to avo i d cr i t i cal ground connect i ons (e . g . , the s i gnal c i rcu i try of the power converter) i n the s i gnal ground plane between the i nput and output capac i tors . it i i sed to keep the planar i nterconnect i on path short ( i. e . , have i nput and output capac i tors close together) . 7 . the output capac i tors should also be connected as closely as poss i ble to the load (or connector) that rece i ves the power (e . g . , a m i croprocessor core) . if the load i s d i str i buted, th e capac i tors should also be d i str i buted, and generally i n pro - port i on to where the load tends to be more dynam i c . 8 . absolutely avo i d cross i ng any s i gnal l i nes over the sw i tch i n power path loop, descr i bed below . power circuitry 9 . the sw i tch i ng power path should be routed on the pcb t o encompass the smallest poss i ble area i n order to m i n i m i ze rad i ated sw i tch i ng no i se energy ( i. e . , emi) . fa i lure to tak e proper precaut i ons often results i n emi problems for the ent i re pc system as well as no i se-related operat i onal proble m i n the power converter control c i rcu i try . the sw i tch i ng powe r path i s the loop formed by the current path through the i nput capac i tors, the power mosfets, and the power schottky d i ode, i f used (see next), i nclud i ng all i ntercon- nect i ng pcb traces and planes . the use of short and w i de i nterconnect i on traces i s espec i ally cr i t i cal i n th i s path for two reasons: i t m i n i m i zes the i nductance i n the sw i tch i ng loop, wh i ch can cause h i gh-energy r i ng i ng, and i t accommo- dates the h i gh current demand w i th m i n i mal voltage loss . 10 . mlc i nput capac i tors should be placed between v in and power ground as close as poss i ble to the sources of the low-s i de mosfets . 11 . to dampen r i ng i ng, an rc snubber c i rcu i t should be place d from the sw node of each phase to ground . 12 . an opt i onal power schottky d i ode (3 aC5 a dc rat i ng) from each lower mosfets source (anode) to dra i n (cat h ode) w i ll help to m i n i m i ze sw i tch i ng power d i ss i pat i on i n the upper mosfets . in the absence of an effect i ve schot tky d i ode, th i s d i ss i pat i on occurs through the follow i ng sequence of sw i tch i ng events . the lower mosfet turns off i n advance of the upper mosfet turn i ng on (necessa r to prevent cross-conduct i on) . the c i rculat i ng current i n the power converter, no longer f i nd i ng a path for curre n through the channel of the lower mosfet, draws cur- rent through the i nherent body d i ode of the mosfet . th e upper mosfet turns on, and the reverse recovery charac - ter i st i c of the lower mosfets body d i ode prevents the dra i n voltage from be i ng pulled h i gh qu i ckly . the upper mosfet then conducts very large current wh i le i t momen- tar i ly has a h i gh voltage forced across i t, wh i ch translates i nto added power d i ss i pat i on i n the upper mosfet . the schottky d i ode m i n i m i zes th i s problem by carry i ng a ma j o r i ty of the c i rculat i ng current when the lower mosfet i s turned off, and by v i rtue of i ts essent i ally nonex i stent reverse recovery t i me . the schottky d i ode has to be con- nected w i th very short copper traces to the mosfet t o be effect i ve . rev. 1 | page 13 of 15 | www.onsemi.com rev. 2 | page 13 of 15 | www.onsemi.com
ADP3164 13 . whenever a power d i ss i pat i ng component (e . g . , a power mosfet) i s soldered to a pcb, the l i beral use of v i as, both d i rectly on the mount i ng pad and i mmed i ately sur- round i ng i t, i s recommended . two i mportant reasons for th i s are: i mproved current rat i ng through the v i as, and i mproved thermal performance from v i as extended to the oppos i te s i de of the pcb where a plane can more read i ly transfer the heat to the a i r . 14 . the output power path, though not as cr i t i cal as the sw i tch- i ng power path, should also be routed to encompass a small area . the output power path i s formed by the current path through the i nductor, the current sens i ng res i stor, the out- put capac i tors, and back to the i nput capac i tors . 15 . for best emi conta i nment, the power ground plane should extend fully under all the power components except the out- put capac i tors . these components are: the i nput capac i tors, the power mosfets and schottky d i odes, the i nductors, the current sense res i stor, and any snubb i ng element that m i ght be added to dampen r i ng i ng . avo i d extend i ng the power ground under any other c i rcu i try or s i gnal l i nes, i nclud i ng the voltage and current sense l i nes . signal circuitry 16 . the output voltage i s sensed and regulated between the fb p i n and the gnd p i n (wh i ch connects to the s i gnal ground plane) . the output current i s sensed (as a voltage) by the cs+ and csC p i ns . in order to avo i d d i fferent i al mode no i se p i ckup i n the sensed s i gnal, the loop area should be small . thus the fb trace should be routed atop the s i gnal ground plane, and the cs+ and csC p i ns (the cs+ p i n should be over the s i gnal ground plane as well) . 17 . the cs+ and csC traces should be kelv i n-connected to the current sense res i stor, so that the add i t i onal voltage drop due to current flow on the pcb at the current sense res i stor connect i ons, does not affect the sensed voltage . rev. 2 | page 14 of 15 | www.onsemi.com
adp316 4 20-lead tssop (ru-20) 20 11 10 1 0 . 256 (6 . 50) 0 . 246 (6 . 25) 0 . 177 (4 . 50) 0 . 169 (4 . 30) pin 1 0 . 260 (6 . 60) 0 . 252 (6 . 40) seating plane 0 . 006 (0 . 15) 0 . 002 (0 . 05) 0 . 0118 (0 . 30) 0 . 0075 (0 . 19) 0 . 0256 (0 . 65) bsc 0 . 0433 (1 . 10) max 0 . 0079 (0 . 20) 0 . 0035 (0 . 090) 0 . 028 (0 . 70) 0 . 020 (0 . 50) 8 0 outline dimensions d i mens i ons shown i n i nches and (mm) . model temperature range package description package option ADP3164jru-reel 0c to 70c thin shrink small outline ru-20 (tssop-20) ADP3164ru-reel7 0c to 70c thin shrink small outline ru-20 (tssop-20) ADP3164ruz-r7 1 0c to 70c thin shrink small outline ru-20 (tssop-20) 1 z = pb-free part on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc reserve s the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc ass ume any liability arising out of the application or use of any product or circuit, and speci cally disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may b e provided in scillc data sheets and/or speci cations can and do vary in different applications and actual performance may vary over time. all operating parameters, includin g ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical im plant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purcha se or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of cers, employees, subsidiaries, af liates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out o f, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/af rmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. literature fulfillment: literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303-675-2175 or 800-344-3860 toll free usa/canada fax : 303-675-2176 or 800-344-3867 toll free usa/canada email : orderlit@onsemi.com n. american technical support : 800-282-9855 toll free usa/canada. europe, middle east and africa technical support : phone: 421 33 790 2910 japan customer focus cente r phone: 81-3-5773-3850 on semiconductor website: www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative publication ordering information

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